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TB62209FG 2005-03-02 1 toshiba bicd processor ic silicon monolithic TB62209FG stepping motor driver ic using pwm chopper type the TB62209FG is a stepping motor driver driven by chopper micro-step pseudo sine wave. the TB62209FG integrates a decoder for clk input in micro steps as a system to facilitate driving a two-phase stepping motor using micro-step pseudo sine waves. micro-step pseudo sine waves are optimal for driving stepping motors with low-torque ripples and at low oscillation. thus, the TB62209FG can easily drive stepping motors with low-torque ripples and at high efficiency. also, TB62209FG consists output steps by dmos (power mos fet), and that makes possible to control the output power dissipation much lower than ordinary ic with bipolar transistor output. the ic supports mixed decay mode for switching the attenuation ratio at chopping. the switching time for the attenuation ratio can be switched in four stages according to the load. features ? bipolar stepping motor can be controlled by a single driver ic ? monolithic bicd ic ? low on-resistance of r on = 0.5 ? (t j = 25c @1.0 a: typ.) ? built-in decoder and 4-bit da converters for micro steps ? built-in isd, tsd, v dd &v m power monitor (reset) circuit for protection ? built-in charge pump circuit (two external capacitors) ? 36-pin power flat package (hsop36-p-450-0.65) ? output voltage: 40 v max ? output current: 1.8 a/phase max ? 2-phase, 1-2 (type 2) phase, w1-2 phase, 2w1-2 phase, 4w1-2 phase, or motor lock mode can be selected. ? built-in mixed decay mode enables specification of four-stage attenuation ratio. ? chopping frequency can be set by external resistors and capacitors. high-speed chopping possible at 100 khz or higher. note: when using the ic, pay attention to thermal conditions. these devices are easy damage by high static voltage. in regards to this, please handle with care. weight: 0.79 g (typ.)
TB62209FG 2005-03-02 2 block diagram 1. overview rese t cw/ccw enable standby d mode 3 d mode 2 d mode 1 clk r s v m ccp c ccp b ccp a mo v dd torque 1 torque 2 mdt 1 mdt 2 chopper osc current level set current feedback ( 2) protection unit tsd protect v re f standby enable v m v dd stepping motor micro-step decoder torque control 4-bit d/a (sine angle control) v rs 1 r s comp 1 v rs 2 r s comp 2 charge pump unit output (h-bridge) 2 ocs cr-clk converter output control (mixed decay control) tsd isd v ddr /v mr protect cr v m
TB62209FG 2005-03-02 3 2. logic unit a/b (c/d unit is the same as a/b unit) function this circuit is used to input from the data pins micro-step current setting data and to transfer them to the subsequent stage. by switching the setup pin, the data in the mixed decay timing table can be overwritten. d mode 1 d mode 2 d mode 3 cw/ccw clk standby mdt 1 mdt 2 decay 2 bit a unit side torque 1 torque 2 data mode micro-step decoder micro-step current data 4 bit a unit side phase 1 bit a unit side current feedback circuit mixed decay circuit output control circuit d/a circuit output control circuit enable reset torque 2 bit decay 2 bit b unit side phase 1 bit b unit side micro-step current data 4 bit b unit side
TB62209FG 2005-03-02 4 3. current feedback circuit and current setting circuit function the current setting circuit is used to set the reference voltage of the output current using the current setting decoder. the current feedback circuit is used to output to the output control circuit the relation between the set current value and output current. this is done by comparing the reference voltage output to the current setting circuit with the potential difference generated when current flows through the current sense resistor connected between r s and v m . the chopping waveform generator circuit to which cr is connected is used to generate clock used as reference for the chopping frequency. note 1: r s comp1 : compares the set current with the output current and outputs a signal when the output current reaches the set current. note 2: r s comp2 : compares the set current with the output current at the end of fast mode during chopping. outputs a signal when the set current is below the output current. waveform shaping circuit v m r s v re f 100 85 70 50 chopping waveform generator circuit cr v rs circuit 1 (detects potential difference between r s and v m ) r s comp circuit 1 (note 1) nf (set current reached signal) v rs circuit 2 (detects potential difference between v m and r s ) r s comp circuit 2 (note 2) rnf (set current monitor signal) < use in fast mode > < use in charge mode > output control circuit mixed decay timing circuit output stop signal (all off) chopping reference circuit 0 current feedback circuit torque control circuit current setting circuit d/a circuit torque 0, 1 current 0-3 decoder unit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 micro-step current setting selector circuit 4-bit d/a circuit
TB62209FG 2005-03-02 5 4. output control circuit, current feedback circuit and current setting circuit note: the standby pins are pulled down in the ic by 100-k ? resistor. when not using the pin, connect it to gnd. otherwise, malfunction may occur. isd circuit output pin v mr circuit v m v ddr circuit v dd tsd circuit current feedback circuit current setting circuit charge pump circuit cop a cr counter cr selector chopping reference circuit micro-step current setting decoder circuit v dd v m logic v ddr : v dd power on reset v mr : v m power on reset isd: current shutdown circuit tsd: thermal shutdown circuit protection circuit charge pump circuit micro-step current setup latch clear signal mixed decay timing table clear signal cop b cop c phase dec a y mode mixed decay timing circuit output reset signal output circuit output circuit charge pump halt signal power supply for upper drive output v h standby nf set current reached signal rnf set current monitor signal output stop signal output control circuit internal stop signal select circuit mixed decay timing charge start u1 u2 l1 l2
TB62209FG 2005-03-02 6 5. output equivalent circuit (a/b unit (c/d unit is the same as a/b unit) note: the diode on the dotted line is parasitic diode. v m b u1 l1 u2 l2 to v m from output control circuit output a output a r s a r rs a m u1 l1 u2 l2 pgnd from output control circuit output b output b r rs b power supply for upper drive output (v h ) u1 u2 l1 l2 output driver circuit phase b r sb v m a power supply for upper drive output (v h ) u1 u2 l1 l2 output driver circuit phase a
TB62209FG 2005-03-02 7 6. input equivalent circuit 1. input circuit (clk, torque, mdt, cw/ccw, data mode, decay mode) 2. input circuit (reset, enable, standby ) 3. v ref input circuit 4. output circuit (mo, protect) v dd v ss out 150 ? gnd v dd v ss in 150 ? to logic ic gnd 100 k ? v dd v ss in 150 ? to logic ic gnd v dd v ss in to d/a circuit gnd 2
TB62209FG 2005-03-02 8 pin assignment (top view) pin assignment for pwm in data mode d mode 1 ga + (out a, a ) d mode 2 ga ? (out a, a ) d mode 3 gb + (out b, b ) cw/ccw gb ? (out b, b ) note: pin assignment above is different at data mode and pwm. 1 d mode 1 2 d mode 2 36 35 cr clk 3 d mode 3 4 cw/ccw 5 v dd 6 v re f 7 nc 8 nc 9 r s b (f in ) 10 r s a 11 nc 12 nc 13 vm 14 standby 15 ccp a 16 ccp b 17 ccp c 18 mo 34 enable 33 out b 32 reset 31 data mode 30 nc 29 out b 28 pgnd (f in ) 27 pgnd 26 out a 25 nc 24 mdt 2 23 mdt 1 22 out a 21 torque2 20 torque1 19 protect TB62209FG
TB62209FG 2005-03-02 9 pin description 1 pin number pin name function remarks 1 d mode 1 2 d mode 2 3 d mode 3 motor drive mode setting pin d mode 3, 2, 1 = lll: same function as that of standby pin llh: motor lock mode lhl: 2-phase excitation mode lhh: 1-2 phase excitation (a) mode hll: 1-2 phase excitation (b) mode hlh: w1-2 phase excitation mode hhl: 2w1-2 phase excitation mode hhh: 4w1-2 phase excitation mode 4 cw/ccw sets motor rotation direction cw: forward rotation ccw: reverse rotation 5 v dd logic power supply connecting pin connect to logic power supply (5 v). 6 v ref reference power supply pin for setting output current connect to supply voltage for setting current. 7 nc not connected not wired 8 nc not connected not wired 9 r s b unit-b power supply pin (connecting pin for power detection resistor) connect current sensing resistor between this pin and v m . f in f in fin logic ground pin connect to power ground. the pin functions as a heat sink. design pattern taking heat into consideration. 10 r s a unit-a power supply pin (pin connecting power detection resistor) connect current sensing resistor between this pin and v m . 11 nc not connected not wired 12 nc not connected not wired pin assignment for pwm in data mode d mode 1 ga + (out a, a ) d mode 2 ga ? (out a, a ) d mode 3 gb + (out b, b ) cw/ccw gb ? (out b, b )
TB62209FG 2005-03-02 10 pin description 2 pin number pin name function remarks 13 v m motor power supply monitor pin connect to motor power supply. 14 standby all-function-initializing and low power dissipation mode pin h: normal operation l: operation halted charge pump output halted 15 ccp a pin connecting capacitor for boosting output stage drive power supply (storage side connected to gnd) connect capacitor for charge pump (storage side) v m and v dd are generated. 16 ccp b pin connecting capacitor for boosting output stage drive power supply connect capacitor for charge pump (charging side) between this pin and ccp c. 17 ccp c (charging side) connect capacitor for charge pump (charging side between this pin and ccp b. 18 mo electrical angle (0 ) monitor pin outputs high level in 4w1-2, 2w1-2, w1-2, or 1-2 phase excitation mode with electrical angle of 0 (phase b: 100%, phase a: 0%). in 2-phase excitation mode, outputs high level with electrical angle of 0 (phase b: 100%, phase a: 100%). 19 protect tsd operation detector pin detects thermal shut down (tsd) and outputs high level. 20 torque 1 21 torque 2 motor torque switch setting pin torque 2, 1 = hh: 100% lh: 85% hl: 70% ll: 50% 22 out a channel a output pin ? 23 mdt 1 24 mdt 2 mixed decay mode setting pins mdt 2, 1 = hh: 100% hl: 75% lh: 37.5% ll: 12.5%
TB62209FG 2005-03-02 11 pin description 3 pin number pin name function remarks 25 nc not connected not wired 26 out a channel a output pin connect to motor 27 pgnd power ground pin connect all power ground pins and v ss to gnd. f in f in logic ground pin the pin functions as a heat sink. design pattern taking heat into consideration. 28 pgnd power ground pin connect all power ground pins to gnd. 29 out b channel b output pin connect to motor 30 nc not connected not wired 31 data mode clock input and pwm h: controls external pwm. l: clk-in mode we recommend this pin normally be used as clk-in mode pin (low). in pwm mode, functions such as constant current control do not operate. 32 reset initializes electrical angle. forcibly initializes electrical angle. at this time we recommend enable pin be set to low to prevent misoperation. h: resets electrical angle. l: normal operation 33 out b channel b output pin ? 34 enable output enable pin forcibly turns all output transistors off. 35 clk inputs clk for determining number of motor rotations. electrical angle is incremented by one for each clk input. clk is reflected at rising edge. 36 cr chopping reference frequency reference pin (for setting chopping frequency) determines chopping frequency.
TB62209FG 2005-03-02 12 1. function of cw/ccw cw/ccw switches the direction of stepping motor rotation. input function h forward (cw) l reverse (ccw) 2. function of mdt 1/mdt 2 mdt 1/mdt 2 specifies the current attenuation speed at constant current control. the larger the rate (%), the larger the attenuation of the current. also, the peak current value (current ripple) becomes larger. (typical value is 37.5%.) mdt 2 mdt 1 function l l 12.5% mixed decay mode l h 37.5% mixed decay mode h l 75% mixed decay mode h h 100% mixed decay mode (fast decay mode) 3. function of torque x torque x changes the current peak value in four steps. used to change the value of the current used, for example, at startup and fixed-speed rotation. torque 2 torque 1 comparator reference voltage h h 100% l h 85% h l 70% l l 50% 4. function of reset (forced initialization of electrical angle) with the clk input method (decoder method), unless clks are counted, except mo, where the electrical angle is at that time is not known. thus, this method is used to forcibly initialize the electrical angle. for example, used to change the excitation mode to another drive mode during output from mo (electrical angle = 0 ). input function h initializes electrical angle to 0 l normal operation
TB62209FG 2005-03-02 13 5. function of enable (output operation) enable forcibly turns off all output transistors at operation. data such as electrical angle and operating mode are all retained. input function h operation enabled (active) l output halted (operation other than output active) 6. function of standby standby halts the charge pump circuit (power supply booster circuit) as well as halting output. we recommend setting to standby mode at power on. (at this time, data on the electrical angle are retained.) input function h operation enabled (active) l output halted (low power dissipation mode) charge pump halted 7. functions of excitation modes excitation mode dm3 dm2 dm1 remarks 1 low power dissipation mode 0 0 0 standby mode charge pump halted 2 motor lock mode 0 0 1 locks only at 0 electrical angle. 3 2-phase excitation mode 0 1 0 45 135 225 315 45 4 1-2 phase excitation (a) 0 1 1 low-torque, 1-bit micro-step change 5 1-2 phase excitation (b) 1 0 0 high-torque, 1-bit micro-step change 6 w1-2 phase excitation 1 0 1 2-bit micro-step change 7 2w1-2 phase excitation 1 1 0 3-bit micro-step change 8 4w1-2 phase excitation 1 1 1 4-bit micro-step change
TB62209FG 2005-03-02 14 8. function of data mode data mode switches external duty control (forced pwm control) and constant current clk-in control. in phase mode, h-bridge can be forcibly inverted and output only can be turned off. constant current drive including micro-step drive can only be controlled in clk-in mode. input function h phase mode l clk-in mode note 1: normally, use clk-in mode. 9. electrical angle setting immediately after initialization in initialize mode (immediately after reset is released), the following currents are set. in low power dissipation mode, the internal decoder continues incrementing the electrical angle but current is not output. note that the initial electrical angle value in 2-phase excitation mode differs from that in nw1-2 (n = 0, 1, 2, 4) phase excitation mode. excitation mode ib (%) ia (%) remarks 1 low power dissipation mode 100 0 electrical angle incremented but no current output 2 motor lock mode 100 0 electrical angle incremented but no motor rotation due to no ia output 3 2-phase excitation 100 100 45 4 1-2 phase excitation (a) 100 0 0 5 1-2 phase excitation (b) 100 0 0 6 w1-2 phase excitation 100 0 0 7 2w1-2 phase excitation 100 0 0 8 4w1-2 phase excitation 100 0 0 note 2: where, ib = 100% and ia = 0%, the electrical angle is 0 . where, ib = 0% and ia = 100%, the electrical angle is + 90 .
TB62209FG 2005-03-02 15 10. function of data mode (phase a mode used for explanation) data mode inputs the external pwm signal (duty signal) and controls the current. functions such as constant current control and overcurrent protector do not operate. use this mode only when control cannot be performed in clk-in mode. ga + ga ? output state (1) l l output off (2) l h a + phase: low a ? phase: high (3) h l a + phase: high a ? phase: low (4) h h output off note: output is off at (1) and (4). d mode 1 ga + (out a, a ) d mode 2 ga ? (out a, a ) d mode 3 gb + (out b, b ) cw/ccw gb ? (out b, b ) u1 l1 u2 l2 off off pgnd off off (1) ? (4) u1 l1 u2 l2 off off on on (note) load pgnd (2) u1 l1 u2 l2 off off on on (note) load pgnd (3)
TB62209FG 2005-03-02 16 maximum ratings (ta = 25c) characteristics symbol rating unit logic supply voltage v dd 7 v motor supply voltage v m 40 v output current (note 1) i out 1.8 a/phase current detect pin voltage v rs v m 4.5 v v charge pump pin maximum voltage (ccp1 pin) v h v m + 7.0 v logic input voltage (note 2) v in to v dd + 0.4 v (note 3) 1.4 power dissipation (note 4) p d 3.2 w operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c junction temperature t j 150 c note 1: perform thermal calculations for the maximum current value under normal conditions. use the ic at 1.5 a or less per phase. the current velue maybe controled according to the ambient temperature or board conditions. note 2: input 7 v or less as v in . note 3: measured for the ic only. (ta = 25c) note 4: measured when mounted on the board. (ta = 25c) ta: ic ambient temperature t opr : ic ambient temperature when starting operation t j : ic chip temperature during operation t j (max) is controlled by tsd (thermal shut down circuit) recommended operating conditions (ta = 0 to 85c, (note 5)) characteristics symbol test condition min typ. max unit power supply voltage v dd ? 4.5 5.0 5.5 v motor supply voltage v m v dd = 5.0 v, ccp1 = 0.22 f, ccp2 = 0.02 f 13 24 34 v output current i out (1) ta = 25c, per phase ? 1.2 1.5 a logic input voltage v in ? gnd ? v dd v clock frequency f clk v dd = 5.0 v ? ? 150 khz chopping frequency f chop v dd = 5.0 v 50 100 150 khz reference voltage v ref v m = 24 v, torque = 100% 2.0 3.0 v dd v current detect pin voltage v rs v dd = 5.0 v 0 1.0 4.5 v note 5: because the maximum value of t j is 120c, recommended maximum current usage is below 120c.
TB62209FG 2005-03-02 17 electrical characteristics 1 (unless otherwise specified, ta = 25c, v dd = 5 v, v m = 24 v) characteristics symbol test circuit test condition min typ. max unit high v in (h) 2.0 v dd v dd + 0.4 input voltage low v in (l) dc data input pins gnd ? 0.4 gnd 0.8 v input hysteresis voltage v in (his) dc data input pins 200 400 700 mv i in (h) data input pins with resistor 35 50 75 i in (h) ? ? 1.0 input current 1 i in (l) dc data input pins without resistor ? ? 1.0 a i dd1 v dd = 5 v (strobe, reset, data = l), reset = l, logic, output all off 1.0 2.0 3.0 power dissipation (v dd pin) i dd2 dc output open, f clk = 1.0 khz logic active, v dd = 5 v, charge pump = charged 1.0 2.5 3.5 ma i m1 output open (strobe, reset, data = l), reset = l, logic, output all off, charge pump = no operation 1.0 2.0 3.0 i m2 output open, f clk = 1 khz logic active, v dd = 5 v, v m = 24 v, output off, charge pump = charged 2.0 4.0 5.0 power dissipation (v m pin) i m3 dc output open, f clk = 4 khz logic active, 100 khz chopping (emulation), output open, charge pump = charged ? 10 13 ma output standby current upper i oh dc v rs = v m = 24 v, v out = 0 v, standby = h, reset = l, clk = l ? 200 ? 150 ? a output bias current upper i ob dc v out = 0 v, standby = h, reset = l, clk = l ? 100 ? 50 ? a output leakage current lower i ol dc v rs = v m = ccpa = v out = 24 v, logic in = all = l ? ? 1.0 a high (reference) v rs (h) v ref = 3.0 v, v ref (gain) = 1/5.0 torque = (h) = 100% set ? 100 ? mid high v rs (mh) v ref = 3.0 v, v ref (gain) = 1/5.0 torque = (mh) = 85% set 83 85 87 mid low v rs (ml) v ref = 3.0 v, v ref (gain) = 1/5.0 torque = (ml) = 70% set 68 70 72 comparator reference voltage ratio low v rs (l) dc v ref = 3.0 v, v ref (gain) = 1/5.0 torque = (l) = 50% set 48 50 52 % output current differential ? i out1 dc differences between output current channels ? 5 ? 5 % output current setting differential ? i out2 dc i out = 1000 ma ? 5 ? 5 % rs pin current i rs dc v rs = 24 v, v m = 24 v, reset = l (reset state) ? 1 2 a r on (d-s) 1 i out = 1.0 a, v dd = 5.0 v t j = 25c, drain-source ? 0.5 0.6 r on (s-d) 1 i out = 1.0 a, v dd = 5.0 v t j = 25c, source-drain ? 0.5 0.6 r on (d-s) 2 i out = 1.0 a, v dd = 5.0 v t j = 105c, drain-source ? 0.6 0.75 output transistor drain-source on-resistance r on (s-d) 2 dc i out = 1.0 a, v dd = 5.0 v t j = 105c, source-drain ? 0.6 0.75 ?
TB62209FG 2005-03-02 18 electrical characteristics 2 (ta = 25c, v dd = 5 v, v m = 24 v, i out = 1.0 a) characteristics symbol test circuit test condition min typ. max unit a = 90 ( 16) ? 100 ? a = 84 ( 15) ? 100 ? a = 79 ( 14) 93 98 ? a = 73 ( 13) 91 96 ? a = 68 ( 12) 87 92 97 a = 62 ( 11) 83 88 93 a = 56 ( 10) 78 83 88 a = 51 ( 9) 72 77 82 a = 45 ( 8) 66 71 76 a = 40 ( 7) 58 63 68 a = 34 ( 6) 51 56 61 a = 28 ( 5) 42 47 52 a = 23 ( 4) 33 38 43 a = 17 ( 3) 24 29 34 a = 11 ( 2) 15 20 25 a = 6 ( 1) 5 10 15 chopper current vector dc a = 0 ( 0) ? ? 0 ? %
TB62209FG 2005-03-02 19 electrical characteristics 3 (unless otherwise specified, ta = 25c, v dd = 5 v, v m = 24 v) characteristics symbol test circuit test condition min typ. max unit v ref input voltage v ref dc v m = 24 v, v dd = 5 v, standby = h, reset = l, output on, clk = 1 khz 2.0 ? v dd v v ref input current i ref dc standby = h, reset = l, output off, v m = 24 v, v dd = 5 v, v ref = 3.0 v 20 35 50 a v ref attenuation ratio v ref (gain) dc v m = 24 v, v dd = 5 v, standby = h, reset = l, output on, v ref = 2.0 to v dd ? 1.0 v 1/4.8 1/5.0 1/5.2 ? tsd temperature (note 1) t j tsd dc v dd = 5 v, v m = 24 v 130 ? 170 c tsd return temperature difference (note 1) ? t j tsd dc t j tsd = 130 to 170c t j tsd ? 50 t j tsd ? 35 t j tsd ? 20 c v dd return voltage v ddr dc v m = 24 v, standby = h 2.0 3.0 4.0 v v m return voltage v mr dc v dd = 5 v, standby = h 2.0 3.5 5.0 v over current protected circuit operation current (note 2) isd dc v dd = 5 v, v m = 24 v ? 3.0 ? a high temperature monitor pin output current i protect dc v dd = 5 v, tsd = operating condition 1.0 3.0 5.0 ma electrical angle monitor pin output current i mo dc v dd = 5 v, electrical angle = 0 (ib = 100%, ia = 0%) 1.0 3.0 5.0 ma v protect (h) dc v dd = 5 v, tsd = operating condition ? ? 5.0 high temperature monitor pin output voltage v protect (l) dc v dd = 5 v, tsd = not operating condition 0.0 ? ? v v mo2 (h) dc v dd = 5 v, electrical angle = except 0 (ib = 100%, ia = except 0% set) ? ? 5.0 electrical angle monitor pin output voltage v mo2 (l) dc v dd = 5 v, electrical angle = 0 (ib = 100%, ia = 0%) 0.0 ? ? v note 1: thermal shut down (tsd) circuit when the ic junction temperature reaches the specified value and the tsd circuit is activated, the internal reset circuit is activated switching the outputs of both motors to off. when the temperature is set between 130 (min) to 170c (max), the tsd circuit operates. when the tsd circuit is activated, the charge pump is halted, and trotect pin outputs v dd voltage. even if the tsd circuit is activated and standby goes h l h instantaneously, the ic is not reset until the ic junction temperature drops ? 20c (typ.) below the tsd operating temperature (hysteresis function). note 2: overcurrent protection circuit when current exceeding the specified value flows to the output, the internal reset circuit is activated, and the isd turns off the output. until the standby signal goes low to high, the overcurrent protection circuit remains activated. during isd, ic turns standby mode and the charge pump halts.
TB62209FG 2005-03-02 20 ac characteristics (ta = 25c, v m = 24 v, v dd = 5 v, 6.8 mh/5.7 ? ) characteristics symbol test circuit test condition min typ. max unit clock frequency f clk ac ? ? ? 120 khz t w (t clk ) ac ? 100 ? ? t wp ac ? 50 ? ? minimum clock pulse width t wn ac ? 50 ? ? ns t r ac output load: 6.8 mh/5.7 ? ? 100 ? t f ac ? ? 100 ? t plh ac clk to out ? 1000 ? t phl ac output load: 6.8 mh/5.7 ? ? 2000 ? t plh ac cr to out ? 500 ? output transistor switching characteristic t phl ac output load: 6.8 mh/5.7 ? ? 1000 ? ns t r ac ? ? 20 ? t f ac ? ? 20 ? t plh ac ? ? 20 ? transistor switching characteristics (mo, protect) t phl ac ? ? 20 ? ns noise rejection dead band time t brank ac i out = 1.0 a 200 300 400 ns cr reference signal oscillation frequency f cr ac c osc = 560 pf, r osc = 3.6 k ? ? 800 ? khz chopping frequency range f chop (min) f chop (max) ac v m = 24 v, v dd = 5 v, output active (i out = 1.0 a) step fixed, ccp1 = 0.22 f, ccp2 = 0.01 f 40 100 150 khz chopping frequency f chop ac output active (i out = 1.0 a), cr clk = 800 khz ? 100 ? khz charge pump rise time t ong ac ccp = 0.22 f, ccp = 0.01 f v m = 24 v, v dd = 5 v, standby = on off ? 100 200 s
TB62209FG 2005-03-02 21 11. current waveform and setting of mixed decay mode at constant current control, in current amplitude (pulsating current) decay mode, a point from 0 to 3 can be set using 2-bit parallel data. nf is the point where the output current reaches the set current value. rnf is the timing for monitoring the set current. the smaller the mdt value, the smaller the current ripple (peak current value). note that current decay capability deteriorates. nf f chop 12.5% mixed decay mode cr pin internal clk waveform charge mode nf: set current value reached slow mode mixed decay timing fast mode current monitored (when set current value > output current) charge mode nf rnf set current value rnf mdt decay mode 0 37.5% mixed decay mode charge mode nf: set current value reached slow mode mixed decay timing fast mode current monitored (when set current value > output current) charge mode rnf set current value decay mode 1 75% mixed decay mode charge mode nf: set current value reached slow mode mixed decay timing fast mode current monitored (when set current value > output current) charge mode rnf set current value mdt nf decay mode 2 fast decay mode fast mode rnf: current monitored (when set current value > output current) charge mode fast mode rnf set current value decay mode 3 100% 75% 50% 25% 0 mdt
TB62209FG 2005-03-02 22 12. current modes (mixed ( slow + fast) decay mode effect) ? current value in increasing (sine wave) sine wave in decreasing (when using mixed decay mode with large attenuation ratio (mdt%) at attenuation) ? sine wave in decreasing (when using mixed decay mode with small attenuation ratio (mdt%) at attenuation) if rnf, current watching point, was the set current value (output current) in the mixed decay mode and in the fast decay mode, there is no charge mode but the slow + fast mode (slow to fast is at mdt) in the next chopping cycle. note: the above charts are schematics. the actual current transient responses are curves. slow slow slow slow fast fast charge charge fast charge fast charge set current value set current value set current value set current value slow slow fast charge fast charge slow fast slow fast charge because current attenuates so quickly, the current immediately follows the set current value. set current value set current value slow fast charge slow fast charge fast slow fast slow because current attenuates slowly, it takes a long time for the current to follow the set current value (or the current does not follow).
TB62209FG 2005-03-02 23 13. mixed decay mode waveform (current waveform) ? when nf is after mixed decay timing ? in mixed decay mode, when the output current > the set current value nf nf 37.5% mixed decay mode i out f chop f chop set current value clk signal input f chop mdt (mixed decay timing) point set current value rnf rnf because the set current value is the output current, no charge mode in the next cycle. (charge cancel function) nf nf 37.5% mixed decay mode i out f chop f chop set current value set current value nf mdt (mixed decay timing) point clk signal input fast decay mode after charge mode rnf nf nf 37.5% mixed decay mode internal cr clk signal i out f chop f chop set current value set current value rnf mdt (mixed decay timing) point
TB62209FG 2005-03-02 24 14. fast decay mode waveform the output current to the motor is in supply voltage mode after the current value set by v ref , r rs , or torque reached at the set current value. f chop clk signal input fast decay mode (100% mixed decay mode) set current value i out nf because the set current value is the output current, charge mode nf fast decay mode in the next cycle. because the set current value is the output current, fast decay mode in the next cycle. (charge cancel function) rnf rnf rnf set current value
TB62209FG 2005-03-02 25 12.5 mixed decay mode 15. clk signal, internal cr clk, and output current waveform (when clk signal is input in slow decay mode) when clk signal is input, the chopping counter (cr-clk counter) is forced to reset at the next cr-clk timing. because of this, compared with a method in which the counter is not reset, response to the input data is faster. the delay time, the theoretical value in the logic portion, is expected to be a one-cycle cr waveform: 5 s at 100 khz chopping. when the cr counter is reset due to clk signal input, charge mode is entered momentarily due to current comparison. note: in fast decay mode, too, charge mode is entered momentarily due to current comparison. clk signal input set current value i out rnf set current value f chop internal cr clk si g nal momentarily enters charge mode reset cr-clk counter here nf rnf mdt nf mdt f chop f chop
TB62209FG 2005-03-02 26 16. strobe signal, internal cr clk, and output current waveform (when clk signal is input in charge mode) 12.5 mixed decay mode clk signal input set current value i out rnf set current value f chop internal cr clk signal momentarily enters charge mode reset cr-clk counter here nf rnf mdt mdt f chop f chop
TB62209FG 2005-03-02 27 12.5 mixed decay mode 17. strobe signal, internal cr clk, and output current waveform (when strobe signal is input in fast decay mode) nf strobe signal input set current value i out rnf set current value f chop internal cr clk signal momentarily enters charge mode reset cr-clk counter here f chop f chop mdt nf rnf mdt mdt
TB62209FG 2005-03-02 28 18. clk signal, internal cr clk, and output current waveform (when clk signal is input in 2 excitation mode) 12.5 mixed decay mode clk signal input f chop reset cr-clk counter here f chop f chop set current value i out rnf set current value nf rnf 0 mdt nf
TB62209FG 2005-03-02 29 current discharge path when enable input during operation in slow mode, when all output transistors are forced to switch off, coil energy is discharged in the following modes: note: parasitic diodes are located on dotted lines. in normal mixed decay mode, the current does not flow to the parasitic diodes. as shown in the figure at right, an output transistor has parasitic diodes. to discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to that in normal operation. as a result, the parasitic diodes are not used. if all the output transistors are forced to switch off, the energy of the coil is discharged via the parasitic diodes. u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on (note) load pgnd u1 l1 u2 l2 off off (note) load pgnd (note) r s pin r rs v m on on load charge mode slow mode forced off mode on r s pin r rs v m r s pin r rs v m power supply off off input enable off
TB62209FG 2005-03-02 30 output transistor operating mode output transistor operation functions clk u1 u2 l1 l2 charge on off off on slow off off on on fast off on on off note: the above table is an example where current flows in the direction of the arrows in the above figures. when the current flows in the opposite direction of the arrows, see the table below. clk u1 u2 l1 l2 charge off on on off slow off off on on fast on off off on u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on on (note) load pgnd u1 l1 u2 l2 (note) load pgnd (note) r s pin r rs v m on on load charge mode slow mode fast mode on r s pin r rs v m r s pin r rs v m off off on off
TB62209FG 2005-03-02 31 power supply sequence (recommended) note 1: if the v dd drops to the level of the v ddr or below while the specified voltage is input to the v m pin, the ic is internally reset. this is a protective measure against malfunction. likewise, if the v m drops to the level of the v mr or below while regulation voltage is input to the v dd , the ic is internally reset as a protective measure against malfunction. to avoid malfunction, when turning on v m or v dd , to input the standby signal at the above timing is recommended. it takes time for the output control charge pump circuit to stabilize. wait up to t ong time after power on before driving the motors. note 2: when the v m value is between 3.3 to 5.5 v, the internal reset is released, thus output may be on. in such a case, the charge pump cannot drive stably because of insufficient voltage. the standby state should be maintained until v m reaches 13 v or more. note 3: since v dd = 0 v and v m = voltage within the rating are applied, output is turned off by internal reset. at that time, a current of several ma flows due to the pass between v m and v dd . when voltage increases on v dd output, make sure that specified voltage is input. v dd (max) v dd (min) v ddr gnd v dd v m v m (min) v mr gnd v m non-reset reset internal reset h l standby input (note 1) takes up to t ong until operable. non-operable area standby
TB62209FG 2005-03-02 32 how to calculate set current this ic controls constant current in clk-in mode. at that time, the maximum current value (set current value) can be determined by setting the sensing resistor (r rs ) and reference voltage (v ref ). 1/5.0 is v ref (gain): v ref attenuation ratio. (for the specifications, see the electrical characteristics.) for example, when inputting v ref = 3 v and torque = 100% to output i out = 0.8 a, r rs = 0.75 ? (0.5 w or more) is required. how to calculate the chopping and osc frequencies at constant current control, this ic chops frequency using the oscillation waveform (saw tooth waveform) determined by external capacitor and resistor as a reference. the TB62209FG requires an oscillation frequency of eight times the chopping frequency. the oscillation frequency is calculated as follows: c) 600 r (c 0.523 1 f cr + = for example, when c osc = 560 pf and r osc = 3.6 k ? are connected, f cr = 813 khz. at this time, the chopping frequency f chop is calculated as follows: f chop = f cr /8 = 101 khz when determining the chopping frequency, make the setting taking the above into consideration. ic power dissipation ic power dissipation is classified into two: power consumed by transistors in the output block and power consumed by the logic block and the charge pump circuit. ? power consumed by the power transistor (calculated with r on = 0.60 ? ) in charge mode, fast decay mode, or slow decay mode, power is consumed by the upper and lower transistors of the h bridges. the following expression expresses the power consumed by the transistors of a h bridge. p (out) = 2 (t r ) i out (a) v ds (v) = 2 i out 2 r on ..............................(1) the average power dissipation for output under 4-bit micro step operation (phase difference between phases a and b is 90) is determined by expression (1). thus, power dissipation for output per unit is determined as follows (2) under the conditions below. r on = 0.60 ? (@ 1.0 a) i out (peak: max) = 1.0 a v m = 24 v v dd = 5 v p (out) = 2 (t r ) 1.0 2 (a) 0.60 ( ? ) = 1.20 (w) ..............................................(2) power consumed by the logic block and im the following standard values are used as power dissipation of the logic block and im at operation. i (logic) = 2.5 ma (typ.): i (i m3 ) = 10.0 ma (typ.): operation/unit i (i m1 ) = 2.0 ma (typ.): stop/unit the logic block is connected to v dd (5 v). im (total of current consumed by the circuits connected to v m and current consumed by output switching) is connected to v m (24 v). power dissipation is calculated as follows: p (logic&im) = 5 (v) 0.0025 (a) + 24 (v) 0.010 (a) = 0.25 (w) ...............(3) thus, the total power dissipation (p) is p = p (out) + p (logic&im) = 1.45 (w) power dissipation at standby is determined as follows: p (standby) + p (out) = 24 (v) 0.002 (a) + 5 (v) 0.0025 (a) = 0.06 (w) for thermal design on the board, evaluate by mounting the ic. 100% ) ( rs r 50%) 70, 85, 100, (torque torque (v) ref v 5.0 1 (max) out i ? = =
TB62209FG 2005-03-02 33 test waveforms ck t ck t ck t p lh t p hl v m gnd t r t f 10% 50% 90% 90% 50% 10% figure 1 timing waveforms and names
TB62209FG 2005-03-02 34 osc-charge delay: because the rising edge level of the osc waveform is used for converting the osc waveform to the internal cr clk, a delay of up to 1.25 ns (@f chop = 100 khz: f cr = 400 khz) occurs between the osc waveform and the internal cr clk. t chop osc-charge delay h l set current osc-fast delay osc (cr) 50% 50% l h h l l charge 50% slow fast output voltage a output voltage a output current cr waveform internal cr clk waveform cr-cr clk delay figure 2 timing waveforms and names (cr and output)
TB62209FG 2005-03-02 35 relationship between drive mode input timing and mo ? if drive mode input changes before mo timing parallel set signal is reflected. ? if drive mode input changes after mo timing parallel set signal occurs after the rising edge of clk, therefore, it is not reflected. the drive mode is changed when the electrical angle becomes 0 . note: the TB62209FG uses the drive mode change reserve method to prevent the motor from step out when changing drive modes. note that the following rules apply when switching drive modes at or near the mo signal output timing. drive mode input internal reflection (1) drive mode input waveform (1) drive mode input internal reflection (2) drive mode input waveform (2) clk waveform mo waveform
TB62209FG 2005-03-02 36 reflecting points of signals point where drive mode setting reflected cw/ccw 2-phase excitation mode 45 (mo) before half-clock of phase b = phase a = 100% at rising edge of clk input 1-2 phase excitation mode w1-2 phase excitation mode 2w1-2 phase excitation mode 4w1-2 phase excitation mode 0 (mo) before half-clock of phase b = 100% at rising edge of clk input other parallel set signals can be changed at any time (they are reflected immediately). recommended point for switching drive mode mo waveform clk waveform when drive mode data switching can be input during mo output (phase data halted) to forcibly switch drive modes, a function to set reset = low and to initialize the electrical angle is required. drive mode reflected
TB62209FG 2005-03-02 37 p d ? ta (package power dissipation) (1) hsop36 r th (j-a) only (96c/w) (2) when mounted on the board (140 mm 70 mm 1.6 mm: 38c/w: typ.) note: r th (j-a) : 8.5c/w ambient temperature ta (c) p d ? ta power dissipation p d (w) (2) (1) 0 0 3.5 25 50 75 100 125 150 0.5 1 1.5 2 2.5 3
TB62209FG 2005-03-02 38 relationship between v m and v h (charge pump voltage) note: v dd = 5 v ccp 1 = 0.22 f, ccp 2 = 0.022 f, f chop = 150 khz (be aware the temperature charges of charge pump capacitor.) v m ? v h (&vcharge up) v h voltage, charge up voltage (v) supply voltage v m (v) charge pump voltage v h = v dd + v m ( = ccp a) (v) 10 20 0 0 v h voltage charge up voltage v m voltage 2 3 10 20 30 40 4 5 6 7 8 9 11 12 13 14 15 16 17 18 21 22 23 24 25 26 19 27 28 29 31 32 33 34 35 36 37 38 39 1 30 40 50 input standby v mr v m voltage maximum rating charge pump voltage usable area recommended operation area
TB62209FG 2005-03-02 39 operation of charge pump circuit ? initial charging (1) when reset is released, t r1 is turned on and t r2 turned off. ccp 2 is charged from ccp 2 via di1. (2) t r1 is turned off, t r2 is turned on, and ccp 1 is charged from ccp 2 via di2. (3) when the voltage difference between v m and v h (ccp a pin voltage = charge pump voltage) reaches v dd or higher, operation halts (steady state). ? actual operation (4) ccp 1 charge is used at f chop switching and the v h potential drops. (5) charges up by (1) and (2) above. output switching initial charging steady state (1) (2) (3) (4) t (5) (4) (5) v h v m v h = v m + v dd = charge pump voltage i1 = charge pump current i2 = gate block power dissipation v dd = 5 v v m = 24 v comparator & controller v m output output h switch i2 ccp 1 0.22 f ccp a ccp b ccp c r 1 v h r s r rs ccp 2 0.01 f di2 di1 di3 v z i1 (2) t r1 t r2 7 (1) (2)
TB62209FG 2005-03-02 40 charge pump rise time t ong : time taken for capacitor ccp 2 (charging capacitor) to fill up ccp 1 (storing capacitor) to v m + v dd after a reset is released. the internal ic cannot drive the gates correctly until the voltage of ccp 1 reaches v m + v dd . be sure to wait for t ong or longer before driving the motors. basically, the larger the ccp 1 capacitance, the smaller the voltage fluctuation, though the initial charge up time is longer. the smaller the ccp 1 capacitance, the shorter the initial charge-up time but the voltage fluctuation is larger. depending on the combination of capacitors (especially with small capacitance), voltage may not be sufficiently boosted. when the voltage does not increase sufficiently, output dmos r on turns lower than the normal, and it raises the temperature. thus, use the capacitors under the capacitor combination conditions (ccp 1 = 0.22 f, c c p 2 = 0.02 f) recommended by toshiba. 50% v dd + v m v m + (v dd 90%) ccp 1 voltage v m 5 v 0 v standby t ong
TB62209FG 2005-03-02 41 external capacitor for charge pump when driving the stepping motor with v dd = 5 v, f chop = 150 khz, l = 10 mh under the conditions of v m = 13 v and 1.5 a, the logical values for ccp 1 and ccp 2 are as shown in the graph below: choose ccp 1 and ccp 2 to be combined from the above applicable range. we recommend ccp 1:ccp 2 at 10:1 or more. (if our recommended values (ccp = 0.22 f, c c p 2 = 0.02 f) are used, the drive conditions in the specification sheet are satisfied. (there is no capacitor temperature characteristic as a condition.) when setting the constants, make sure that the charge pump voltage is not below the specified value and set the constants with a margin (the larger ccp 1 and ccp 2, the more the margin). some capacitors exhibit a large change in capacitance according to the temperature. make sure the above capacitance is obtained under the usage environment temperature. ccp 1 capacitance ( f) ccp 1 ? ccp 2 ccp 2 capacitance ( f) 0.05 0 0 recommended value 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.1 0.15 0.2 0.25 0.35 0.4 0.45 0.5 0.3 applicable range
TB62209FG 2005-03-02 42 (1) low power dissipation mode low power dissipation mode turns off phases a and b, and also halts the charge pump. operation is the same as that when the standby pin is set to low. (2) motor lock mode motor lock mode turns phase b output only off with phase a off. from reset, with ia = 0 and ib = 100%, the normal 4w1-2 phase operating current is output. use this mode when you want to hold (lock) the rotor at any desired value. (3) 2-phase excitation mode electrical angle 360 = 4 clks note: 2-phase excitation has a large load change due to motor induced electromotive force. if a mode in which the current attenuation capability (current control capability) is small is used, current increase due to induced electromotive force may not be suppressed. in such a case, use a mode in which the mixed decay ratio is large. we recommend 37.5% mixed decay mode as the initial value (general condition). 100 0 phase b phase a [%] ? 100 step ib (%) 2-phase excitation mode (typ.a) ia (%) 100 0 100
TB62209FG 2005-03-02 43 (4) 1-2 phase excitation mode (a) electrical angle 360 = 8 clk ib (%) 1-2 phase excitation mode (typ.a) ia (%) 0 100 100 phase b phase a 100 0 [%] ? 100 step mo cl k
TB62209FG 2005-03-02 44 (5) 1-2 phase excitation mode (b) electrical angle 360 = 8 clk ib (%) 1-2 phase excitation mode (typ.b) ia (%) 0 100 100 71 71 mo phase b phase a 100 0 [%] ? 100 step 71 ? 71 clk
TB62209FG 2005-03-02 45 (6) w1-2 phase excitation mode electrical angle 360 = 16 clk ib (%) w1-2 phase excitation mode (2-bit micro step) ia (%) 0 100 100 71 71 38 92 38 92 100 0 [%] ? 100 step ? 92 ? 71 ? 38 38 92 71 phase a phase b
TB62209FG 2005-03-02 46 (7) 2w1-2 phase excitation mode electrical angle 360 = 32 clk ib (%) 2w 1-2 phase excitation mode (3-bit micro step) ia (%) 92 100 0 100 98 71 71 38 38 92 98 83 56 20 83 56 20 100 0 [%] ? 100 step ? 83 ? 38 ? 20 38 88 71 ? 92 ? 98 ? 71 ? 56 20 56 96 phase a phase b
TB62209FG 2005-03-02 47 (8) 4w1-2 phase excitation mode electrical angle 360 = 64 clk ? 100 ste ? 98 0 ? 96 ? 88 ? 92 ? 77 ? 71 ? 56 ? 63 ? 47 ? 38 ? 29 ? 20 ? 10 ? 83 10 20 29 38 47 56 63 71 77 83 88 92 96 98 100 [ % ] phase a phase b
TB62209FG 2005-03-02 48 4-bit micro step output current vector locus (normalizing each step to 90 ) for input data, see the current function examples. ia (%) ib (%) x = 16 0 100 10 20 29 38 47 56 63 71 77 83 88 92 96 98 100 10 20 29 38 47 56 63 77 71 88 83 98 96 92 x = 0 x = 15 x = 14 x = 13 x = 12 x = 11 x = 10 x = 9 x = 8 x = 7 x = 6 x = 5 x = 4 x = 3 x = 2 x = 1 cw ccw x x
TB62209FG 2005-03-02 49 recommended application circuit the values for the devices are all recommended values. for values under each input condition, see the above-mentioned recommended operating conditions. note: adding bypass capacitors is recommended. make sure that gnd wiring has only one contact point, and to design the pattern that allows the heat radiation. to control setting pins in each mode by sw, make sure to pull down or pull up them to avoid high impedance. to input the data, see the section on the recommended input data. because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing output lines, v dd (v m ) lines, and gnd lines. m r osc = 3.6 k ? c osc = 560 pf v ref ab v m r rs a a b a b r rs b v ss (f in ) protect mo dmode 3 dmode 2 dmode 1 mdt 1 mdt 2 standby p-gnd reset cw/ccw enable clk data mode v dd cr v ref ab 3 v 1 f sgnd r rs a 0.66 ? stepping motor 0.66 ? r rs b sgnd sgnd sgnd 5 v 10 f ccp c ccp b ccp a ccp 2 0.01 f ccp 1 0.22 f data mode torque 2 torque 1 open open 0 v 0 v 5 v 0 v 24 v sgnd 100 f 5 v 0 v 5 v 0 v 5 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v 0 v 5 v pgnd
TB62209FG 2005-03-02 50 package dimensions weight: 0.79 g (typ.)
TB62209FG 2005-03-02 51 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the re sponsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 030619eba restrictions on product use

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